The present invention relates to circuits and methods for reducing power consumption in integrated circuits (IC), and more particularly, circuits and methods for reducing power consumption in Power-On Reset (POR) circuits in the IC.
A POR circuit detects the power applied to an IC and generates a reset impulse that goes to different parts of the IC to place the IC into a known state. An IC can have multiple POR circuits with slightly different functions, where the multiple POR circuits are connected to different areas of the IC.
In addition, an IC with multiple power supplies requires different POR circuits to monitor each of the power supplies. Typical POR circuits consume static DC (Direct Current) power, even though they are active only during the reset phase. POR circuits include circuits that use the output from a bandgap bias generation circuit as a reference voltage or as a voltage level sensor, and circuits using the transistor threshold voltage as a reference voltage or as a voltage level sensor. The POR circuits stay powered, even after the POR sequence ends, draining power although the POR circuits serve no useful purpose during the normal operation of the IC. This situation can change if the power supply drifts below a given threshold, because the IC will restart the power up sequence, thus reactivating the different POR circuits.
The continuous power drainage by POR circuits poses a problem for low-power designs. It is in this context that embodiments of the invention arise.